Examples of the use of Makefiles

MAKEFILES is a directory of C programs which contains some examples of how a "makefile" can be used to manage the compilation and loading of a C program.


A makefile is usually stored in a file named makefile.

The purpose of a makefile is to record or infer the commands necessary to compile and load a program (or, more generally, to "build" a program or object that depends on objects), to intelligently automate this task, and to efficiently update all objects that depend on an object that has itself just been updated.

The most natural example for which a makefile is useful would involve the relationship between several text files containing C routines (with extension ".c"), the object files created by compiling separately each C file (with extension ".o"), and the executable program that can be created by loading them all together (which, by default, is called "a.out", but which we will rename to "c_simple".

We suppose we start with C source code files c_simple.c, midpoint.c, and f.c, and an include file c_simple.h. If we wished to build the executable c_simple, we need to create c_simple.o, midpoint.o, f.o, and then load them together, and rename the result to c_simple.

The "dependencies" or relationships between these files can be thought of as follows:

        c_simple needs c_simple.o, midpoint.o and f.o.
          The commands to create c_simple are
          gcc c_simple.o midpoint.o sub2.o
          mv a.out c_simple
        c_simple.o needs c_simple.c and c_simple.h.
          The command to create c_simple.o is
          gcc -c c_simple.c

        midpoint.o needs midpoint.c and c_simple.h.
          The command to create midpoint.o is
          gcc -c midpoint.c

        f.o needs f.c and c_simple.h.
          The command to create f.o is
          gcc -c f.c

The corresponding makefile records these relationships. Each dependency line lists a "target" (something you want to make), followed by a colon, and then a list of the components on which that target depends. There follow one or more command lines that tell how to put the components together to make the target. Note that each command line must begin with a TAB character. We will use the symbol --TAB--> to suggest this. Here is what the makefile would look like

        c_simple : c_simple.o midpoint.o f.o
        --TAB--> gcc c_simple.o midpoint.o f.o
        --TAB--> mv a.out c_simple
        c_simple.o : c_simple.c c_simple.h
        --TAB--> gcc -c c_simple.c
        midpoint.o : midpoint.c c_simple.h
        --TAB--> gcc -c midpoint.c
        f.o : f.c c_simple.h
        --TAB--> gcc -c f.c

To create the program, type make c_simple. If you just edited midpoint.c and want only to recompile it, type make midpoint.o. But if you just edited midpoint.c, and you want to recompile it, and then also recreate the program, then type make c_simple. The make program will notice that midpoint.c has been updated, and automatically recompile it, and then rebuild c_simple.


The computer code and data files described and made available on this web page are distributed under the GNU LGPL license.


MAKEFILES is available in a C version, a C++ version and a FORTRAN77 version and a FORTRAN90 version.


  1. Robert Mecklenburg,
    Managing Projects with GNU Make,
    O'Reilly, 2004,
    ISBN: 0596006101.
  2. Steve Talbot,
    Managing Projects with Make,
    O'Reilly, 1990,
    ISBN: 0-937-175-18-8.

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Last revised on 04 December 2006.